#ifndef _RTL8373_ASICDRV_H_
#define _RTL8373_ASICDRV_H_

#include <rtk_types.h>
#include <rtk_error.h>
#include <rtl8373_reg_definition.h>

#define RTL8373_REGBITLENGTH               (32)
#define RTL8373_REGDATAMAX                  (0xFFFFFFFF)
#define RTL8373_REG_ADDR_STEP             (4)
#define RTL8373_PHYBITLENGTH               (16)
#define RTL8373_PHYDATAMAX                  (0xFFFF)

#define RTL8373_QOS_RATE_INPUT_MAX         (0x1FFFF * 8)
#define RTL8373_QOS_RATE_INPUT_MAX_HSG     (0x989680)
#define RTL8373_QOS_PPS_INPUT_MAX          (0xE310B8)
#define RTL8373_PKTLENMAX                   (0x3FFF)

#define RTL8373_PORTNO                     (10)
#define RTL8373_PORTIDMAX                  (RTL8373_PORTNO-1)
#define RTL8373_PMSKMAX                    ((1<<(RTL8373_PORTNO))-1)
#define RTL8373_PORTMASK                   (0x3FF)

#define RTL8373_PRIMAX                       (7)
#define RTL8373_DSCPMAX                    (63)

#define RTL8373_VIDMAX                      (0xFFF)
#define RTL8373_FIDMAX                      (15)
#define RTL8373_MSTIMAX                    (15)

#define RTL8373_VLAN_4KTABLE_LEN              (1)
#define RTL8373_VLAN_BUSY_CHECK_NO         (10)

#define RTL8373_C2SIDXMAX                  (127)

#define RTL8373_SVIDXNO                     (0x1000)
#define RTL8373_SVIDXMAX                   (RTL8373_SVIDXNO-1)

#define RTL8373_LOGGINGNO                    (64)
#define RTL8373_LOGGINGMAX                   (RTL8373_LOGGINGNO-1)

#define RTL8373_QUEUENO                  (8)
#define RTL8373_QIDMAX                     (RTL8373_QUEUENO-1)

#define RTL8373_GPIO_PIN_NUM            (64)
#define RTL8373_GPIO_MAX_PIN_NUM    (GPIO_PIN_NUM -1)


#define RTL8373_METERNO                     (64)
#define RTL8373_METERMAX                   (RTL8373_METERNO-1)
#define RTL8373_METERBUCKETSIZEMAX         (0xFFFFFFF)

#define RTL8373_PHY_BUSY_CHECK_COUNTER     (1000)
#define RTL8373_MACSEC_POLLCNT     (1000)

#define RTL8373_QOS_GRANULARTY_MAX              (0x7FFFF)
#define RTL8373_QOS_GRANULARTY_LSB_MASK    (0xFFFF)
#define RTL8373_QOS_GRANULARTY_LSB_OFFSET  (0)
#define RTL8373_QOS_GRANULARTY_MSB_MASK     (0x70000)
#define RTL8373_QOS_GRANULARTY_MSB_OFFSET  (16)

#define RTL8373_QOS_GRANULARTY_UNIT_KBPS   (8)

#define RTL8373_QOS_RATE_INPUT_MAX         (0x1FFFF * 8)
#define RTL8373_QOS_RATE_INPUT_MAX_HSG     (0x989680)
#define RTL8373_QOS_RATE_INPUT_MIN        (8)
#define RTL8373_QOS_PPS_INPUT_MAX          (0xE310B8)
#define RTL8373_QOS_PPS_INPUT_MIN          1

#define RTL8373_QUEUE_MASK                 (0xFF)

#define RTL8373_DISABLE_L2_LEARN_NO             (2)
#define RTL8373_DISABLE_L2_LEARN_MAX            (RTL8373_DISABLE_L2_LEARN_NO -1)


/* the above macro is generated by genDotH */
#define RTL8370UG_VALID_REG_NO               (5000)

/*=======================================================================
 *  Enum
 *========================================================================*/
enum RTL8370UG_TABLE_ACCESS_EXECUTE
{
    TB_NOT_EXECUTE = 0,
    TB_EXECUTE,
};


enum RTL8370UG_TABLE_ACCESS_OP
{
    TB_OP_READ = 0,
    TB_OP_WRITE
};

enum RTL8370UG_TABLE_ACCESS_TARGET
{
    TB_TARGET_ACLRULE = 1,
    TB_TARGET_ACLACT,
    TB_TARGET_CVLAN,
    TB_TARGET_L2,
    TB_TARGET_IGMP_GROUP,
    TB_TARGET_HSA,
    TB_TARGET_HSB
};

/* the above macro is generated by genDotH */
#define RTL8373_VALID_REG_NO               5000

/*=======================================================================
 *  Enum
 *========================================================================*/


#define RTL8373_TABLE_ACCESS_REG_DATA(op, target)    ((op << 3) | target)

/*=======================================================================
 *  Structures
 *========================================================================*/


#ifdef __cplusplus
extern "C" {
#endif
extern ret_t rtl8373_setAsicRegBit(rtk_uint32 reg, rtk_uint32 bit, rtk_uint32 value);
extern ret_t rtl8373_getAsicRegBit(rtk_uint32 reg, rtk_uint32 bit, rtk_uint32 *pValue);

extern ret_t rtl8373_setAsicRegBits(rtk_uint32 reg, rtk_uint32 bits, rtk_uint32 value);
extern ret_t rtl8373_getAsicRegBits(rtk_uint32 reg, rtk_uint32 bits, rtk_uint32 *pValue);

extern ret_t rtl8373_setAsicReg(rtk_uint32 reg, rtk_uint32 value);
extern ret_t rtl8373_getAsicReg(rtk_uint32 reg, rtk_uint32 *pValue);

#ifdef __cplusplus
}
#endif



#endif /*#ifndef _RTL8373_ASICDRV_H_*/

